The present invention relates generally to data communications, and more particularly, to a system and method for achieving timing synchronization by using a network timing reference circuit in a timing synchronization feedback control loop.
In the field of data communications a transceiver, or modem, is used to convey information from one location to another. Digital subscriber line (DSL) technology now enables DSL transceivers to more rapidly communicate data than previously possible with purely analog modems. DSL transceivers communicate by modulating a baseband signal carrying encoded digital data, converting the modulated digital data signal to an analog signal, and transmitting the analog signal over a conventional copper wire pair using techniques that are known in the art. These known techniques include mapping the information to be transmitted into a multi-dimensional multi-level signal space constellation and slicing the received constellation to recover the transmitted information. The constellation can include both analog and digital information or only digital information.
In the above mentioned communications environment, a central office DSL transceiver is located at a telephone company central office location. Connected to the DSL transceiver via a conventional copper wire pair is a suitably configured remote DSL transceiver. The remote transceiver resides at a location, such as a residence or a business location. Before the central office transceiver can exchange information with the remote transceiver, clock timing and synchronization between the central office transceiver and a network master clock should be established.
Timing and synchronization are fundamental to any digital transmission and switching network. In a digital transmission system, timing is encoded with the transmitted signal using a network master clock, such as a T1 or E1 clock as a reference clock. As such, the central office transceiver must recover system timing and synchronization from this system clock. Once frequency synchronization between the central office transceiver and the network clock is achieved, the central office transceiver can identify frame boundaries of downstream data signals designated for further transmission to the remote transceiver. In addition, the central office transceiver can identify frame boundaries of upstream data signals received from the remote transceiver that may be designated for further transmission to other network connected devices.
In the aforementioned communications environment, synchronization is provided in a master-slave relationship such that the network timing (e.g., a T1 clock) is the master allowing it to provide timing information to all the slave data transmission systems connected to the network. Each transceiver connected to the network must be synchronized to the network system clock.
A common technique for achieving timing synchronization between the network clock and the central office transceiver is based upon the use of an external framer, which performs a bit stuffing operation. In this arrangement the aggregate bit stream has a higher data rate than the input data rate from the network. This data rate relationship accommodates the additional stuffing and framing bits. Bits are stuffed (inserted) or removed from the incoming data stream until a clock rate derived from the incoming data stream is equal to that of the input data rate from the network. This bit stuffing operation permits the transceiver to derive a local clock with a frequency that tracks the frequency of the network clock. The stuffed bits are inserted at fixed locations of each frame so that they can be identified and removed at the remote transceiver. Unfortunately, this technique requires the use of additional bits thus the technique consumes bandwidth that would otherwise be available for data transmissions.
Another known technique for achieving network timing synchronization is to lock the central office transceiver to the system clock using a voltage controlled oscillator (VCO) in conjunction with a phase locked loop (PLL). In this arrangement, the PLL synchronizes the local VCO output with the remote network clock. This ensures that the local VCO output is at the same frequency and in phase with the network clock. The local VCO output can then be used as a local clock. The local VCO output is fed back to a phase detector. The phase detector compares both the external or master clock input signal with the local VCO output. If there is a difference in frequency or phase between the two inputs, the phase detector generates an error signal. The error signal may be filtered and amplified to produce an error-correcting signal. This error-correcting signal may be applied at the local VCO to adjust the frequency and phase of the local VCO output. This hardware solution uses additional circuitry that adds system cost and complexity.
In light of the foregoing, The present invention takes advantage of a hardware circuit typically implemented on a digital signal processor (DSP) to implement a network timing reference transport mechanism to a remotely located transceiver in an xDSL application. A network timing reference unit (NTRU) is used as a phase detector embedded in a loopback system that permits synchronization of a DSL integrated circuit to an external reference clock. The system and method of the present invention provide for the synchronization of one or more derived clocks to a network system clock without the use of external bit or symbol framing or additional external circuit components. The system may be implemented in a combination of firmware and software that uses a loopback configuration that ensures after initial acquisition the locally generated clock and all clock signals derived from the local clock signal dynamically track any frequency and phase variation of the external reference clock.
A network timing reference unit generates a phase error offset by clocking data into comparison registers in response to the maximum counter values. Subsequent counter values are mathematically combined to generate a series of phase offset samples. The phase error samples may be stored and further manipulated over time to generate a phase error correction signal for use in a clock synchronization control loop. The network timing reference unit may comprise a counter, an input register, a first comparison register, a second comparison register, and an adder. The present invention provides a method for generating a phase offset. In its broadest terms, the method can be described as: receiving a network clock and a local clock; using a higher-frequency replica of the local clock to generate a counter input signal; recording counter output values at intervals responsive to the network clock; comparing subsequent counter values at intervals responsive to a maximum value of the counter; and combining subsequent counter values to generate a series of phase error samples.
Other features and advantages of the present invention will become apparent to one with skill in the art upon examination of the following drawings and detailed description. It is intended that all such additional features and advantages be included herein within the scope of the present invention, as defined in the appended claims.